1. Field of the Invention
The present invention relates to an address transition detecting (hereinafter referred to as "ATD") circuit of a semiconductor memory device, and more particularly to an ATD circuit capable of generating an ATD pulse of a constant width independent of variation of a power supply voltage.
2. Background of the Prior Art
Semiconductor memory devices integrated on a semiconductor substrate such as static random access memories (SRAMs), dynamic random access memories (DRAMs) and nonvolatile memories utilize an ATD pulse signal to control the precharge and voltage equalization of a bit line, driving of a logic circuit in a sense amplifier, and driving of various logic circuits, The ATD pulse signal has a high or low logic of a predetermined width at a rising edge or falling edge of an address signal, and the pulse width of the ATD pulse signal must be properly set to allow the memory device to have a rapid access speed without causing malfunction. However, a conventional ATD circuit for generating the ATD pulse signal increases or decreases the pulse width of the ATD pulse signal according to the variation of a power supply voltage. Moreover, due to the pulse width of the ATD pulse signal decreased according to the excess power supply voltage over a normal operating voltage, the ATD pulse signal having an unnecessarily great pulse width is generated at the power supply voltage of a normal operating voltage level, thereby lengthening the access time of the memory device. This is because the conventional ATD circuit consists of logic circuits formed of MOS transistors which have a propagation delay time varied in accordance with the level of the power supply voltage. The ATD circuit of a conventional semiconductor memory device having the above-stated problems will be described with reference to FIG. 1.
Referring to FIG. 1, the ATD circuit of the conventional semiconductor memory device includes a first delay line 11 for delaying and inverting 1-bit address signal supplied into an input terminal 10, and a NOR gate 26 for receiving the address signal from the input terminal 10 and the inverted and delayed address signal from the first delay line 11. The NOR gate 26 compares the address signal with the inverted and delayed address signal to generate a pulse of a high logic whose pulse width is as much as the delay time of the first delay line 11 at the falling edge of the latter address signal. The ATD circuit further includes an inverter 18 for inverting the address signal from the input terminal 10, a second delay line 13 for inverting and delaying the inverted address signal from the inverter 18 to its original state and delaying it, and a NOR gate 28 for comparing the logic of the delayed address signal from the second delay line 13 with that of the inverted address signal from the inverter 18. The NOR gate 28 generates a pulse of a high logic whose width is as much as the delay time of the second delay line 13 at the rising edge of the address signal, and supplies the generated pulse of high logic to a third NOR gate 30. The third NOR gate 30 mixes the pulse from the second NOR gate 28 with that from the first NOR gate 26 and inverts the result, of the mixing, to generate an ATD pulse signal having a width as much as the delay time of the first and second delay lines 11 and 13 at the falling and rising edges of the address signal and output the ATD pulse signal via an output terminal 32. The first and second delay lines 11 and 13 include a series circuit consisting of three inverters 12.about.16 and 20.about.24, respectively, for fully securing the precharge period and voltage equalization period of a bit line in the semiconductor memory device. The inverters 12.about.16 and 20.about.24 are formed of MOS transistors (not shown) having shorter propagation delay time as the power supply voltage exceeds the normal operating voltage. Also, the first and second delay lines 11 and 13 have unnecessarily longer delay time at the normal operating voltage in order to fully secure the precharge period and voltage equalization period of the bit line in the semiconductor memory device at the power supply voltage which exceeds the normal operating voltage. In case that the power supply voltage maintains the normal operating voltage, the ATD pulse signal has an unnecessarily greater pulse width owing to the long delay times of the first and second delay lines 11 and 13.
As described above, to the ATD circuit of the conventional semiconductor memory device, in which the pulse width of the ATD pulse signal is determined by the delay time of the delay line, generates the ATD pulse signal having the unnecessarily greater pulse width at the normal operating voltage due to the delay lines formed of the MOS transistors, which have the propagation delay time decreased in accordance with the increased amount of the power supply voltage, to slow down the access speed of the semiconductor memory device,